R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1192

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

23. Serial Peripheral Interface (HSPI)
Note:
Rev.1.00 Jan. 10, 2008 Page 1160 of 1658
REJ09B0261-0100
Bit
3
2
1
0
*
Bit Name
RXFL
RXOW
TXFN
TXFL
These bits are readable/writable bits. Writing 0 initializes these bits to the initial values
of respective bits, while writing 1 is ignored.
Initial
Value
0
0
0
0
R/W
R/W*
R
R
R
Description
Receive Buffer Overrun Warning Flag
This status flag is set to 1 when a new serial data
transfer has started before the previous received data is
read from SPRBR. The RXOW remains set to 1 until
writing 0 to this bit position.
If RXOW= 1 and ROIE = 1, an interrupt is generated.
Receive Buffer Full Status Flag
This status flag indicates that new data is available in
the SPRBR and has not yet been read. It is set to 1
when the shift register contents are loaded into the
SPRBR in the end of a serial bus transfer. This bit is
cleared to 0 by reading SPRBR.
Transmit Complete Status Flag
This status flag indicates that the last transmission has
been completed. It is set to 1 when SPTBR is ready to
accept data from the peripheral bus. This bit is cleared
to 0 by writing data to SPTBR.
If TXFN = 1 and TFIE = 1, an interrupt is generated.
Transmit Buffer Full Status Flag
This status flag indicates the SPTBR stores data that
has not been transmitted. It is set to 1 when SPTBR is
written with data from the peripheral bus. This bit is
cleared to 0 when SPTBR is ready to accept data from
the peripheral bus.