R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1023

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

20.3.13 CL Control Register (CLCR)
CLCR is in the CL register block and specifies the CL operating mode.
Initial value:
Initial value:
Bit
31 to 9
8 to 4
3
2
R/W:
R/W:
BIt:
BIt:
2. Setting Method When Setting Values in Succession
3. The input Y/U/V pointers and output pointers must be set to point to addresses on 32-
4. Two commands can be received. If the next command is written when the command
Bit Name
⎯
CL_DA
⎯
CL_OD
When setting values in this register in succession, the CL module is able to receive the
next command while the CL_CFF bit in CLSR is 0. To perform processing by changing
the command alone, just set the new command in this register.
byte boundaries. If not, the lower address is regarded as 0.
FIFO is full, the commands stored in the command FIFO are retained and the next
command is ignored.
31
15
⎯
⎯
⎯
⎯
0
0
30
14
⎯
⎯
⎯
⎯
0
0
29
13
⎯
⎯
⎯
⎯
0
0
Initial
Value
All 0
All 0
0
0
28
⎯
⎯
12
⎯
⎯
0
0
R/W
⎯
R/W
⎯
R/W
27
⎯
⎯
11
⎯
⎯
0
0
26
10
⎯
⎯
⎯
⎯
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Specifies output data alignment.
The correspondence between the alignment and
specified value is shown in the following table.
Reserved
This bit is always read as 0. The write value should
always be 0.
Specifies output access size (access size for output)
0: 4 bytes
1: 32 bytes
25
⎯
⎯
⎯
⎯
0
9
0
R/W
24
⎯
⎯
0
8
0
20. Graphics Data Translation Accelerator (GDTA)
R/W
23
⎯
⎯
0
7
0
CL_DA
Rev.1.00 Jan. 10, 2008 Page 991 of 1658
R/W
22
⎯
⎯
0
6
0
R/W
21
⎯
⎯
0
5
0
R/W
20
⎯
⎯
0
4
0
19
⎯
⎯
⎯
⎯
0
3
0
REJ09B0261-0100
CL_OD
R/W
18
⎯
⎯
0
2
0
CL_OA
R/W
17
⎯
⎯
0
1
0
CL_MD
R/W
16
⎯
⎯
0
0
0