R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1061

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ANBGV

Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ANBGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
20.5
In the GDTA, there are four types of interrupt sources. There are three interrupt flags for CL
processing end, MC processing end, and CL/MC errors, used to identify interrupt sources. The
interrupt enable bit allows generation of interrupt requests.
CL errors and MC errors use a common GAERI interrupt.
Table 20.10 GDTA Interrupt Request
20.6
The GDTA performs data alignment conversion of input data, output data, and RAM 0/1 data
using an endian signal (pin MD8) or using GDTA internal registers.
Table 20.11 shows the correspondence between data alignment conversion patterns and the
settings of DRCL_CTL, DWCL_CTL, DRMC_CTL, DWMC_CTL, DCP_CTL, and DID_CTL.
Table 20.11 GDTA Data Alignment Conversion
Note:
Interrupt Source
CL_END interrupt
MC_END interrupt
CL_ERR interrupt
MC_ERR interrupt
DTAM
0
0
1
1
1
1
1
1
1
*
Interrupt Processing
Data Alignment
DTSA
H'00
H'00
H'00
H'01
H'01
H'01
H'10
H'10
H'11
For the data alignment pattern numbers, refer to figure 20.8.
DTUA
H'00
H'00
H'00
H'01
H'10
H'11
H'01
H'10
H'01
Interrupt Flag
CL_END
MC_END
CL_ERR or MC_ERR
Little (MD8)
0
1
*
*
*
*
*
*
*
Data Alignment Conversion Pattern Remarks
CP3 (2)
CP3 (1)
CP3 (2)
CP1 (1)
CP2 (1)
CP3 (1)
CP1 (2)
CP2 (2)
CP1 (3)
Enable Bit
CL_ENEN
MC_ENEN
CL_EREN
MC_EREN
20. Graphics Data Translation Accelerator (GDTA)
Rev.1.00 Jan. 10, 2008 Page 1029 of 1658
Description
CL processing ended
MC processing ended
CL error occurred
MC error occurred
REJ09B0261-0100

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