R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 227

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7.7.4
The UTLB address array is allocated to addresses H'F600 0000 to H'F60F FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and VPN, D, V, and ASID to be written to the address array are
specified in the data field.
In the address field, bits [31:20] have the value H'F60 indicating the UTLB address array and the
entry is specified by bits [13:8]. Bit [7] that is the association bit (A bit) in the address field
specifies whether address comparison is performed in a write to the UTLB address array.
In the data field, bits [31:10] indicate VPN, bit [9] indicates D, bit [8] indicates V, and bits [7:0]
indicate ASID.
The following three kinds of operation can be used on the UTLB address array:
1. UTLB address array read
2. UTLB address array write (non-associative)
3. UTLB address array write (associative)
VPN, D, V, and ASID are read into the data field from the UTLB entry corresponding to the
entry set in the address field. In a read, associative operation is not performed regardless of
whether the association bit specified in the address field is 1 or 0.
VPN, D, V, and ASID specified in the data field are written to the UTLB entry corresponding
to the entry set in the address field. The A bit in the address field should be cleared to 0.
When a write is performed with the A bit in the address field set to 1, comparison of all the
UTLB entries is carried out using the VPN specified in the data field and ASID in PTEH. The
usual address comparison rules are followed, but if a UTLB miss occurs, the result is no
operation, and an exception is not generated. If the comparison identifies a UTLB entry
corresponding to the VPN specified in the data field, D and V specified in the data field are
written to that entry. This associative operation is simultaneously carried out on the ITLB, and
if a matching entry is found in the ITLB, V is written to that entry. Even if the UTLB
comparison results in no operation, a write to the ITLB is performed as long as a matching
entry is found in the ITLB. If there is a match in both the UTLB and ITLB, the UTLB
information is also written to the ITLB.
UTLB Address Array
Rev.1.00 Jan. 10, 2008 Page 195 of 1658
7. Memory Management Unit (MMU)
REJ09B0261-0100