R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 142
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 142 of 1694
- Download datasheet (9Mb)
5. Exception Handling
(6)
• Sources:
• Transition address: VBR + H'0000100
Rev.1.00 Jan. 10, 2008 Page 110 of 1658
REJ09B0261-0100
ITLB_protection_violation_exception()
{
}
⎯ Word data access from other than a word boundary (2n +1)
⎯ Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3)
⎯ Quadword data access from other than a quadword data boundary (8n +1, 8n + 2, 8n +3, 8n
⎯ Access to area H'80000000 to H'FFFFFFFF in user mode
⎯ The MMCAW bit in EXPMASK is 0, and the IC/OC memory mapped associative write is
Data Address Error
TEA = EXCEPTION_ADDRESS;
PTEH.VPN = PAGE_NUMBER;
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = H'0000 00A0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'0000 0100;
(Except MOVLIA)
+ 4, 8n + 5, 8n + 6, or 8n + 7)
Areas H'E0000000 to H'E3FFFFFF and H'E5000000 to H'E5FFFFFF can be accessed in
user mode. For details, see section 7, Memory Management Unit (MMU) and section 9,
On-Chip Memory.
performed. For details of memory mapped associative write, see section 8.6.5, Memory-
Mapped Cache Associative Write Operation.
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