R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 704

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 672 of 1658
REJ09B0261-0100
Channel Name
0
1
2
3
0, 1
2, 3
4, 5
6
7
DMA source address register B0
DMA destination address register
B0
DMA transfer count register B0
DMA source address register B1
DMA destination address register
B1
DMA transfer count register B1
DMA source address register B2
DMA destination address register
B2
DMA transfer count register B2
DMA source address register B3
DMA destination address register
B3
DMA transfer count register B3
DMA extended resource selector 0
DMA extended resource selector 1
DMA extended resource selector 2
DMA source address register 6
DMA destination address register 6
DMA transfer count register 6
DMA channel control register 6
DMA source address register 7
DMA destination address register 7
DMA transfer count register 7
DMA channel control register 7
Abbrev.
SARB0
DARB0
TCRB0
SARB1
DARB1
TCRB1
SARB2
DARB2
TCRB2
SARB3
DARB3
TCRB3
DMARS0 H'0000
DMARS1 H'0000
DMARS2 H'0000
SAR6
DAR6
TCR6
CHCR6
SAR7
DAR7
TCR7
CHCR7
Power-on
Reset
by PRESET
Pin/WDT/
H-UDI
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
H'4000 0000 H'4000 0000
Undefined
Undefined
Undefined
H'4000 0000 H'4000 0000
Manual
Reset
by
WDT/Multiple
Exception
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
H'0000
H'0000
H'0000
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Sleep
by SLEEP
instruction
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Deep Sleep
by SLEEP
instruction
(DSLP = 1)
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Module
Standby
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained