R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 399

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

11.4.2
BCR is a 32-bit readable/writable register that specifies the function, bus cycle state, etc for each
area. BCR is initialized to H'0000 0000 in big endian mode and to H'8000 0000 in little endian
mode by a power-on reset, however, not initialized by a manual reset.
Initial value:
Initial value:
Bit
31
30
29 to 27 ⎯
Note: *
R/W:
R/W:
BIt:
BIt:
Bus Control Register (BCR)
Bit Name
ENDIAN
MASTER
END
IAN
The initial values of bits 31 and 30 depend on the states of the external pins MODE8 and MODE9, respectively.
31
15
x*
—
R
R
0
MAS
R/W
TER
CNT
HIZ
30
14
x*
R
0
Initial
Value
x
x
All 0
29
13
—
—
R
R
0
0
28
—
12
—
R
R
0
0
27
—
11
—
R
R
0
0
R/W
R
R
R
DPUP
R/W
26
10
—
R
0
0
Description
Endian Flag
The value on the external pin (MODE8) that sets the
endian mode is sampled and reflected in this bit at a
power-on reset by the PRESET pin. This bit determines
the endian for all spaces.
0: Indicates that a low level is on the MODE8 pin at a
1: Indicates that a high level is on the MODE8 pin at a
Master/Slave Flag
The value on the external pin (MODE9) that sets
master/slave is sampled and reflected in this bit at a
power-on reset by the PRESET pin. This bit specifies
master/slave for all spaces.
0: Indicates that a high level is on the MODE9 and the
1: Indicates that a high level is on the MODE9 and the
Reserved
These bits are always read as 0. The write value should
always be 0.
25
—
—
LSI has been configured as master.
LSI has been configured as slave.
R
R
power-on reset and the LSI has been configured for
big endian.
power-on reset and the LSI has been configured for
little endian.
0
9
0
OPUP
R/W
24
—
R
0
8
0
R/W
23
—
R
0
7
0
DACKBST[3:0]
Rev.1.00 Jan. 10, 2008 Page 367 of 1658
R/W
R/W
22
0
6
0
11. Local Bus State Controller (LBSC)
R/W
R/W
21
0
5
0
R/W
R/W
20
0
4
0
ASYNC[6:0]
R/W
19
—
R
0
3
0
REJ09B0261-0100
R/W
18
—
R
0
2
0
BREQ
R/W
R/W
17
EN
0
1
0
DMA
R/W
R/W
BST
16
0
0
0