R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 549

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10. Writing to DBMRCNT issues the MRS command to the SDRAM and sets the various
11. Writing to the CMD bits in DBCMDCNT issues the PALL command.
12. Writing to the CMD bits in DBCMDCNT issues the REF command. Following that, writing to
13. Writing to DBMRCNT issues the MRS command to the SDRAM. Other than the parameter
14. After a wait of at least 200 clock cycles has elapsed via the software, writing to DBMRCNT
15. A 1 (access enabled) is set in the ACEN bit in the SDRAM operation enable register (DBEN).
16. Enter settings in the SDRAM refresh control register 1 (DBRFCNT1) and the SDRAM refresh
17. Set the ARFEN bit in DBRFCNT0 to 1 (automatic issue of auto-refresh enabled). Normal
12.5.4
Self-refreshing helps to reduce the amount of power consumed by the SDRAM and makes it
possible to change the clock frequency and stop the clock.
Also, using the self-refresh operation in combination with power supply control makes it possible
to operate in power supply backup mode, with all power supplies other than that of the SDRAM
off. For details on power supply backup mode, refer to section 12.5.10, DDR2-SDRAM Power
Supply Backup Function.
(1)
If it is not necessary to access the SDRAM, the SDRAM can be put in self-refresh mode to reduce
power consumption while still retaining data contents.
Shifting to self-refresh mode is done by writing 1 to the self-refresh enable bit (SRFEN) in the
SDRAM refresh control register 0 (DBRFCNT0). Self-refresh mode can be cancelled by writing 0
to the SRFEN bit.
parameters. At this point, the operating mode is set to normal mode, the DLL reset is set to
reset, the burst length is set to 4, and the burst type is set to sequential. The additive latency
should be set to 0, and CAS latency and write recovery times should be set to match the
settings of DBTR0 and DBTR1.
the CMD bits in DBCMDCNT is done once again and the REF command is issued.
that cancels a DLL reset in the SDRAM, the parameters are the same as the values set in item
10 above.
issues the EMRS(1) command to the SDRAM and issues the OCD default command.
Subsequently, writing is done to DBMRCNT, the EMRS(1) command is issued, and the OCD
calibration mode exit command is issued.
control register 2 (DBRFCNT2), and set the auto-refresh interval and other parameters.
access is subsequently enabled.
Self-Refreshing (without Stopping the Clock)
Self-Refresh Operation
Rev.1.00 Jan. 10, 2008 Page 517 of 1658
12. DDR2-SDRAM Interface (DBSC2)
REJ09B0261-0100