R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 805
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 805 of 1694
- Download datasheet (9Mb)
WDTBCNT is an 18-bit counter that is incremented by the peripheral clock. If the period of
peripheral clock Pck is represented as tPck (ns), the overflow time of WDTBCNT is expressed as
follows.
WDTCNT is a 12-bit counter that is incremented each time WDTBCNT overflows. The time until
WDTCNT overflows becomes maximum when 0 is written to all the bits in WDTST. If the period
of peripheral clock Pck is represented as tPck (ns), the maximum overflow time of WDTCNT is
expressed as follows.
The time until WDTCNT overflows becomes minimum when H'5A00 0001 is written to WDTST.
In this case, the overflow time is equal to that of WDTBCNT.
For example, if the peripheral clock frequency is 50 MHz, tPck is 20 ns and the overflow times are
as follows.
16.4.5
Setting the overflow value in WDTBST clears WDTBCNT to 0, and setting the overflow value in
WDTST clears WDTCNT to 0.
2
2
Overflow time of WDTBCNT: 0.262
Maximum overflow time of WDTCNT: 1.073
18
12
Clearing WDT Counters
[bit]
[bit]
×
× (
tPck [ns] = 0.262
0.262
×
tPck) [ms] = 1.073
×
tPck [ms]
×
×
20 = 5.24 [ms]
tPck [s]
×
20 = 21.46 [s]
Rev.1.00 Jan. 10, 2008 Page 773 of 1658
16. Watchdog Timer and Reset (WDT)
REJ09B0261-0100
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