R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 75

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

2.7
2.7.1
To accelerate the processing speed, the instruction prefetching capability of this LSI has been
significantly enhanced from that of the SH-4. Therefore, in the case when a code in memory is
rewritten and attempted to be executed immediately, there is increased possibility that the code
before being modified, which has already been prefetched, is executed.
To ensure execution of the modified code, one of the following sequence of instructions should be
executed between the code rewriting instruction and execution of the modified code.
(1)
The target for the ICBI instruction can be any address within the range where no address error
exception occurs.
(2)
All instruction cache areas corresponding to the modified codes should be invalidated by the ICBI
instruction. The ICBI instruction should be issued to each cache line. One cache line is 32 bytes.
(3)
All operand cache areas corresponding to the modified codes should be written back to the main
memory by the OCBP or OCBWB instruction. Then all instruction cache areas corresponding to
the modified codes should be invalidated by the ICBI instruction. The OCBP, OCBWB, and ICBI
instruction should be issued to each cache line. One cache line is 32 bytes.
Note: Self-modifying code is the processing which executes instructions while dynamically
SYNCO
ICBI @Rn
SYNCO
ICBI @Rn
OCBP @Rm or OCBWB @Rm
SYNCO
ICBI @Rn
When the Codes to be Modified are in Non-Cacheable Area
When the Codes to be Modified are in Cacheable Area (Write-Through)
When the Codes to be Modified are in Cacheable Area (Copy-Back)
rewriting the codes in memory.
Usage Notes
Notes on Self-Modifying Code
Rev.1.00 Jan. 10, 2008 Page 43 of 1658
2. Programming Model
REJ09B0261-0100