R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 318

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10. Interrupt Controller (INTC)
(6)
INTMSK1 is a 32-bit readable and conditionally writable register that sets masking for IRL
interrupt requests. To clear the mask setting for the interrupt, write 1 to the corresponding bit in
INTMSKCLR1. Writing 0 to the bits in INTMSK1 has no effect. By reading this register once
after writing to this register or after clearing the mask by setting IMTMSKCLR1, the time length
necessary for reflecting the register value can be assured (the value read is reflected to the mask
status).
Rev.1.00 Jan. 10, 2008 Page 286 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31
30
29 to 24 ⎯
23 to 0
R/W:
R/W:
Interrupt Mask Register 1 (INTMSK1)
Bit:
Bit:
Name
IM10
IM11
⎯
IM10 IM11
R/W
31
15
⎯
R
1
0
R/W
30
14
⎯
R
1
0
Initial
Value
1
1
All 1
All 0
29
⎯
13
⎯
R
R
1
0
28
12
⎯
⎯
R
R
1
0
R/W
R/W
R/W
R
R
27
11
⎯
⎯
R
R
1
0
26
10
⎯
⎯
R
R
1
0
Description
Mask setting for all IRL3 to
IRL0 interrupt sources
when pins IRQ/IRL3 to
IRQ/IRL0 operate as an
encoded interrupt input.
Mask setting for all IRL7 to
IRL4 interrupt sources
when pins IRQ/IRL7 to
IRQ/IRL4 operate as an
encoded interrupt input.
Reserved
These bits are always read as 1. The write value
should always be 1.
Reserved
These bits are always read as 0. The write value
should always be 0.
25
⎯
⎯
R
R
1
9
0
24
⎯
⎯
R
R
1
8
0
23
⎯
⎯
R
R
0
7
0
22
⎯
⎯
R
R
0
6
0
21
⎯
⎯
R
R
0
5
0
[When read]
0: The interrupt is
1: The interrupt is
[When written]
0: No effect
1: Masks the interrupt
20
⎯
⎯
R
R
0
4
0
masked.
accepted.
19
⎯
⎯
R
R
0
3
0
18
⎯
⎯
R
R
0
2
0
17
⎯
⎯
R
R
0
1
0
16
⎯
⎯
R
R
0
0
0