R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1564

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

31. Register List
Notes: 1. The interrupt source registers (INTREQ) are readable and conditionally writable
Rev.1.00 Jan. 10, 2008 Page 1532 of 1658
REJ09B0261-0100
Module
Name
GPIO
UBC
H-UDI
2. The NMI flag control register (NMIFCR) is readable and conditionally writable register.
3. To clear the flag, the HE and TE bits in CHCR can be read as 1, and then, 0 can be
4. To clear the flag, the AE and NMIF bits in DMAOR can be read as 1, and then, 0 can be
5. To clear a flag, only writing 0 to bits 7 to 4, 1, and 0 is valid.
6. To clear a flag, only writing 0 to bit 0 is valid.
Name
Port N pull-up control register
Input pin pull-up control register 1
Input pin pull-up control register 2
Peripheral module select register 1
Peripheral module select register 2
Match condition setting register 0
Match operation setting register 0
Match address setting register 0
Match address mask setting register 0
Match condition setting register 1
Match operation setting register 1
Match address setting register 1
Match address mask setting register 1
Match data setting register 1
Match data mask setting register 1
Execution count break register 1
Channel match flag register
Break control register
Instruction register
Interrupt source register
Boundary scan register
Bypass register
registers. For details, refer to section 10.3.1 (4), Interrupt Source Register (INTREQ).
For details, refer to section 10.3.1 (11), NMI Flag Control Register (NMIFCR).
written to.
written to.
Abbreviation R/W
PNPUPR
PPUPR1
PPUPR2
P1MSELR
P2MSELR
CBR0
CRR0
CAR0
CAMR0
CBR1
CRR1
CAR1
CAMR1
CDR1
CDMR1
CETR1
CCMFR
CBCR
SDIR
SDINT
SDBSR
SDBPR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
⎯
⎯
P4 Area
Address
H'FFE7 0058
H'FFE7 0060
H'FFE7 0062
H'FFE7 0080
H'FFE7 0082
H'FF200000
H'FF200004
H'FF200008
H'FF20000C
H'FF200020
H'FF200024
H'FF200028
H'FF20002C
H'FF200030
H'FF200034
H'FF200038
H'FF200600
H'FF200620
H'FC11 0000
H'FC11 0018
⎯
⎯
Area 7
Address
H'1FE7 0058
H'1FE7 0060
H'1FE7 0062
H'1FE7 0080
H'1FE7 0082
H'1F200000
H'1F200004
H'1F200008
H'1F20000C
H'1F200020
H'1F200024
H'1F200028
H'1F20002C
H'1F200030
H'1F200034
H'1F200038
H'1F200600
H'1F200620
H'1C11 0000
H'1C11 0018
⎯
⎯
Access
Size
32
32
32
32
⎯
⎯
8
16
16
16
16
32
32
32
32
32
32
32
32
32
16
16