R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 733

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14.4
When DMA transfer is requested, the DMAC starts transfer according to the determined channel
priority. When the transfer end conditions are satisfied, the DMAC ends transfer. Transfer
requests have three modes: auto-request mode, external request mode, and on-chip peripheral
module request mode. Bus modes can be chosen from burst mode or cycle steal mode.
14.4.1
DMA transfer requests are basically generated in either the data transfer source or data transfer
destination, but they can also be generated in external devices or on-chip peripheral modules that
are neither the transfer source nor the transfer destination.
Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral
module request. The transfer request is selected by bits RS3 to RS0 in CHCR0 to CHCR11, and
DMARS0 to DMARS5, according to DMA channels.
(1)
Auto-request mode is a mode that automatically generates transfer request signal in the DMAC
when there is no transfer request signal from an external source, like memory-to-memory transfer
or a transfer between memory and an on-chip peripheral module that cannot generate transfer
request. When the DE bit in CHCR, the DME bit in DMAOR0 for channels 0 to 5, and the DME
bit in DMAOR1 for channels 6 to 11 are set to 1, transfers are started. In channels 0 to 5, the AE
and NMIF bits in DMAOR0 should be all 0. In channels 6 to 11, the AE and NMIF bits in
DMAOR1 should be all 0.
(2)
External request mode is a mode that starts transfer by the transfer request signal (DERQ0 to
DREQ3) from the external device of this LSI. This mode is valid in only channels 0 to 3. Table
14.4 shows the external request mode settings. While DMA transfer is enabled (DE = 1, DME = 1,
TE = 0, AE = 0, NMIF = 0), DMA transfer starts when DREQ is input.
Table 14.4 External Request Mode Setting with RS Bits
RS3
0
Auto-Request Mode
External Request Mode
RS2
0
Operation
DMA Transfer Requests
CHCR
RS1
0
0
RS0
Address Mode
Dual address mode
Transfer Source
Any
14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 701 of 1658
Transfer Destination
Any
REJ09B0261-0100