R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 449
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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complement mode. To access the Device Control Register and Alternate Status Register, use a
CPU byte access (do not use a DMA transfer), and to access the Data Register, use the CPU word
access (do not use a DMA transfer). To access the Data Port use a DMA transfer. When a CPU
byte access is executed, CE1x is negated and CE2x is asserted (x = A, B). When a CPU word
access is executed, CE1x is asserted and CE2x is negated. When a DMA access is executed, CE1x
and CE2x are negated. The setting example of the DMAC (by DMA channel control register
CHCR) is external request, burst mode, level detection, overrun 0, DACK output to the
correspondent PCMCIA connected area. Set the DACKBST bit in BCR of the corresponding
DMA transfer channel to 1, so that the corresponding DACK signal is asserted from the beginning
to the end of the DMA transfer cycle. Even if the corresponding DREQ signal is negated during
the transfer, the DACK signal is not negated. When DMA transfer that outputs DACK is made to
access an area where ATA complement mode is set, neither CE1x nor CE2x is asserted.
Figure 11.15 CExx and DACKn Output during DMA Transfer in Access to Space where
In this example, the number of DMA transfers = 4, transfer size = word, and DACKn is active-low.
CExx
DACKn
CExx
DACKn
ATA Complement Mode Is Set
ATA complement mode, DACKBST = 1
IO card interface, DACKBST = 0
Rev.1.00 Jan. 10, 2008 Page 417 of 1658
11. Local Bus State Controller (LBSC)
REJ09B0261-0100
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