R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 385
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 385 of 1694
- Download datasheet (9Mb)
Notes: 1. CE2A is an output pin when the TYPE bits in CS5BCR are set to B'100.
Pin Name
MODE11,
MODE12
DACK0*
DACK1*
DACK2*
DACK3*
2. CE2B is an output pin when the TYPE bits in CS6BCR are set to B'100.
3. The polarity of DACK0 to DACK3 can be selected by the AL bit in CHCR0 to CHCR3
3
3
3
3
(the initial value selects active-low). For details, see section 14, Direct Memory Access
Controller (DMAC).
Function
Bus Mode
Switching
DMAC0
Acknowledge
Signal
DMAC1
Acknowledge
Signal
DMAC2
Acknowledge
Signal
DMAC3
Acknowledge
Signal
I/O
I
O
O
O
O
Description
Signals for switching buses: local bus, PCI bus
or DU bus
Bus modes for D63 to D32 and WE7 to WE4 are
switched at a power-on reset by the PRESET
pin
MODE11: Multiplexed with SCIF4_SCK (SCIF
MODE12: Multiplexed with DACK3 (DMAC0
Data acknowledge in DMAC channel 0
Multiplexed with Port K1 (GPIO input/output)
Data acknowledge in DMAC channel 1
Multiplexed with Port K0 (GPIO input/output)
Data acknowledge in DMAC channel 2
Multiplexed with SCIF2_TXD (SCIF output),
MMCCMD (MMCIF input/output), SIOF_TXD
(SIOF output) and Port K5 (GPIO input/output)
Data acknowledge in DMAC channel 3
Multiplexed with SCIF2_SCK (SCIF
input/output), MMCDAT (MMCIF input/output),
SIOF_SCK (SIOF input/output) and Port K4
(GPIO input/output)
input/output), FD3 (FLCTL
input/output), Port N0 (GPIO output)
output), CE2B (LBSC output), Port L0
(GPIO output)
Rev.1.00 Jan. 10, 2008 Page 353 of 1658
11. Local Bus State Controller (LBSC)
REJ09B0261-0100
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