R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 190

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7. Memory Management Unit (MMU)
Rev.1.00 Jan. 10, 2008 Page 158 of 1658
REJ09B0261-0100
Bit
25, 24
23 to 18
17, 16
15 to 10
9
8
Bit Name
⎯
URB
⎯
URC
SQMD
SV
Initial
Value
All 0
000000
All 0
000000
0
0
R/W
R
R/W
R
R/W
R/W
R/W
Description
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
UTLB Replace Boundary
These bits indicate the UTLB entry boundary at which
replacement is to be performed. Valid only when URB ≠
0.
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
UTLB Replace Counter
These bits serve as a random counter for indicating the
UTLB entry for which replacement is to be performed
with an LDTLB instruction. This bit is incremented each
time the UTLB is accessed. If URB > 0, URC is cleared
to 0 when the condition URC = URB is satisfied. Also
note that if a value is written to URC by software which
results in the condition of URC > URB, incrementing is
first performed in excess of URB until URC = H'3F.
URC is not incremented by an LDTLB instruction.
Store Queue Mode
Specifies the right of access to the store queues.
0: User/privileged access possible
1: Privileged access possible (address error exception
Single Virtual Memory Mode/Multiple Virtual Memory
Mode Switching
When this bit is changed, ensure that 1 is also written
to the TI bit.
0: Multiple virtual memory mode
1: Single virtual memory mode
in case of user access)