DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 516

• Manufacturer Part Number: DF2170VTE33
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2170VTE33; HD64F2170VTE33

Rev. 2.00, 03/04, page 482 of 534
Register Name
DMA source address register_2 DMSAR_2
DMA destination address
register_2
DMA transfer count register_2
DMA mode control register_2
DMA address control register_2 DMACR_2
DMA source address register_3 DMSAR_3
DMA destination address
register_3
DMA transfer count register_3
DMA mode control register_3
DMA address control register_3 DMACR_3
USB transfer control register
IRQ enable register
Interrupt control register A
Interrupt control register B
Interrupt control register C
IRQ status register
IRQ sense control register H
IRQ sense control register L
Address break control register
Break address register A
Break address register B
Break address register C
IRQ sense port select register
Port function control register 1
Port function control register 3
Port 1 data direction register
Port 2 data direction register
Port 3 data direction register
Port 4 data direction register
Port 5 data direction register
Port 6 data direction register
Port 7 data direction register
Abbreviation
DMDAR_2
DMTCR_2
DMMDR_2
DMDAR_3
DMTCR_3
DMMDR_3
USTCR
IER
ICRA
ICRB
ICRC
ISR
ISCRH
ISCRL
ABRKCR
PBARA
PBARB
PBARC
ISSR
PFCR1
PFCR3
P1DDR
P2DDR
P3DDR
P4DDR
P5DDR
P6DDR
P7DDR
Number
of Bits
32
32
32
16
16
32
32
32
16
16
16
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Address
H'FED0
H'FED4
H'FED8
H'FEDC
H'FEDE
H'FEE0
H'FEE4
H'FEE8
H'FEEC
H'FEEE
H'FEF0
H'FF46
H'FF4A
H'FF4B
H'FF4C
H'FF4D
H'FF5D
H'FF60
H'FF62
H'FF70
H'FF71
H'FF72
H'FF73
H'FF74
H'FF75
H'FF76
H'FF48
H'FF49
H'FF54
H'FF55
H'FF56
H'FF57
DMAC_2
DMAC_2
DMAC_3
Module
DMAC_2
DMAC_2
DMAC_2
DMAC_3
DMAC_3
DMAC_3
DMAC_3
DMAC
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
Data
Width
16
16
16
16
16
16
16
16
16
16
16
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Access
States
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2