DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 160

• Manufacturer Part Number: DF2170VTE33
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2170VTE33; HD64F2170VTE33

6.6.7
If the RAST bit is set to 1 in DRAMCR, the RAS signal goes low from the beginning of the T
state, and the row address hold time and DRAM read access time are changed relative to the fall of
the RAS signal. Use the optimum setting according to the DRAM connected and the operating
frequency of this LSI. Figure 6.24 shows an example of the timing when the RAS signal goes low
from the beginning of the T
If a row address hold time or read access time is necessary, making a setting in bits RCD1 and
RCD0 in DRACCR allows from one to three T
to be inserted between the T
the column address is output. Use the setting that gives the optimum row address signal hold time
relative to the falling edge of the RAS signal according to the DRAM connected and the operating
frequency of this LSI. Figure 6.25 shows an example of the timing when one T
Rev. 2.00, 03/04, page 126 of 534
Figure 6.24 Example of Access Timing when RAS Signal Goes Low from Beginning
Read
Write
Row Address Output State Control
φ
Address bus
Data bus
Data bus
(
(
(
(
(
,
)
)
)
)
)
r
r
state.
cycle, in which the RAS signal goes low, and the T
of T
T
p
Row address
r
State (CAST = 0)
rw
states, in which row address output is maintained,
T
r
High
High
T
c1
Column address
T
c2
rw
c1
state is set.
cycle, in which
r