DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 25

• Manufacturer Part Number: DF2170VTE33
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2170VTE33; HD64F2170VTE33

Figure 6.41 Example of Timing when Precharge Time after Self-Refreshing is Extended
Figure 6.42 Example of DACK Output Timing when DDS = 1 (RAST = 0, CAST = 0) .......... 141
Figure 6.43 Example of DACK Output Timing when DDS = 0 (RAST = 0, CAST = 1) .......... 142
Figure 6.44 Example of Idle Cycle Operation (Consecutive Reads in Different Areas) ............ 143
Figure 6.45 Example of Idle Cycle Operation (Write after Read) .............................................. 144
Figure 6.46 Example of Idle Cycle Operation (Read after Write) .............................................. 145
Figure 6.47 Relationship between Chip Select (CS) and Read (RD).......................................... 145
Figure 6.48 Example of DRAM Full Access after External Read (CAST = 0) .......................... 146
Figure 6.49 Example of Idle Cycle Operation in RAS Down Mode
Figure 6.50 Example of Timing when Write Data Buffer Function is Used .............................. 150
Section 7 DMA Controller (DMAC)
Figure 7.1 Block Diagram of DMAC ......................................................................................... 155
Figure 7.2 Example of Timing in Dual Address Mode............................................................... 173
Figure 7.3 Data Flow in Single Address Mode........................................................................... 174
Figure 7.4 Example of Timing in Single Address Mode ............................................................ 175
Figure 7.5 Example of Timing in Cycle Steal Mode .................................................................. 177
Figure 7.6 Examples of Timing in Burst Mode .......................................................................... 178
Figure 7.7 Examples of Timing in Normal Transfer Mode ........................................................ 178
Figure 7.8 Example of Timing in Block Transfer Mode ............................................................ 179
Figure 7.9 Example of Repeat Area Function Operation............................................................ 180
Figure 7.10 Example of Repeat Area Function Operation in Block Transfer Mode .................. 181
Figure 7.11 DMTCR Update Operations in Normal Transfer Mode and
Figure 7.12 Procedure for Changing Register Settings in Operating Channel ........................... 185
Figure 7.13 Example of Channel Priority Timing ...................................................................... 187
Figure 7.14 Examples of Channel Priority Timing..................................................................... 188
Figure 7.15 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer .......................... 189
Figure 7.16 Example of Normal Transfer Mode (Burst Mode) Transfer.................................... 190
Figure 7.17 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer
Figure 7.18 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer
Figure 7.19 Example of Block Transfer Mode (Cycle Steal Mode) Transfer............................. 191
Figure 7.20 Example of Normal Mode Transfer Activated by DREQ Pin Falling Edge............ 192
Figure 7.21 Example of Block Transfer Mode Transfer Activated by DREQ Pin
Figure 7.22 Example of Normal Mode Transfer Activated by DREQ Pin Low Level............... 194
Figure 7.23 Example of Block Transfer Mode Transfer Activated by DREQ Pin Low Level ... 195
Figure 7.24 Example of Single Address Mode (Byte Read) Transfer ........................................ 196
by 2 States................................................................................................................ 140
(Consecutive Reads in Different Areas)
(IDLE1 = 0, IDLE0 = 1, IDLC1 = 0, IDLC0 = 1, RAST = 0, and CAST = 0)........ 147
Block Transfer Mode............................................................................................... 184
(Transfer Source: USB) ........................................................................................... 190
(Transfer Destination: USB).................................................................................... 191
Falling Edge............................................................................................................. 193
Rev. 2.00, 03/04, page xxiii of xxxii