DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 368

• Manufacturer Part Number: DF2170VTE33
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2170VTE33; HD64F2170VTE33

12.3.16 FIFO Clear Register 0 (FCLR0)
FCLR0 is a one-shot register used to clear the FIFO for each endpoint. Writing 1 to a bit clears the
data in the corresponding FIFO.
For IN FIFO, writing 1 to a bit in FCLR0 clears the data for which the corresponding bit in the
packet enable register is not set to 1 after data write, or data that is validated by setting the
corresponding bit in the packet enable register.
For OUT FIFO, writing 1 to a bit in FCLR0 clears data that has been received. EP2 having a dual-
FIFO configuration is cleared by entire FIFOs. Similarly, as for EP1 FIFO with a dual-FIFO
configuration, the only side currently selected is cleared. Note that this trigger does not clear the
corresponding interrupt flag. Accordingly, care must be taken not to clear data that is currently
being received or transmitted.
Bits 6, 5, and 0 are also used as the status bits. The function of the status bit is described in the
lower column of the bit description.
Rev. 2.00, 03/04, page 334 of 534
Bit
31 to 7 
6
Bit Name
EP3CLR
Initial
Value
All 0
0
R/W
W
R
W
Description
Reserved
The write value should always be 0.
EP3 Clear
1 is written when clearing EP3 IN FIFO. Writing 0 is
invalid and no operation is performed.
EP3 FIFO Clear Status
[Setting condition]
This bit is set to 1 when the EP3 FIFO is forcibly cleared
by the FCLR register. When this bit is set to 1, access to
the EP3 FIFO is prohibited. This bit is cleared to 0
automatically after the FIFO is internally cleared. Confirm
that this bit is cleared to 0 and then wait for at least four
cycles, before accessing to the EP3.
[Clearing condition]
This bit cannot be cleared because this bit is a status bit.