DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 122

• Manufacturer Part Number: DF2170VTE33
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2170VTE33; HD64F2170VTE33

6.3.2
CSACR selects whether or not the assertion period of the basic bus interface chip select signals
(CSn) and address signals is to be extended. Extending the assertion period of the CSn and address
signals allows flexible interfacing to external I/O devices.
Rev. 2.00, 03/04, page 88 of 534
Bit
7
6
5
4
3
2
1
0
Bit Name
CSXH3
CSXH2
CSXH1
CSXH0
CSXT3
CSXT2
CSXT1
CSXT0
CS Assertion Period Control Register (CSACR)
Initial
Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
CS and Address Signal Assertion Period Control 1
These bits specify whether or not the T
inserted (see figure 6.2). When an area for which the
CSXHn bit is set to 1 is accessed, a one-state T
in which only the CSn and address signals are
asserted, is inserted before the normal access cycle.
0: In area n basic bus interface access, the CSn and
1: In area n basic bus interface access, the CSn and
CS and Address Signal Assertion Period Control 2
These bits specify whether or not the T
inserted (see figure 6.2). When an area for which the
CSXTn bit is set to 1 is accessed, a one-state T
in which only the CSn and address signals are
asserted, is inserted before the normal access cycle.
0: In area n basic bus interface access, the CSn and
1: In area n basic bus interface access, the CSn and
address assertion period (T
address assertion period (T
address assertion period (T
address assertion period (T
h
h
t
t
) is not extended
) is extended
) is not extended
) is extended
h
t
cycle is to be
cycle is to be
(n = 3 to 0)
t
h
cycle,
cycle,