DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 418

MCU 3V 256K 100-TQFP

DF2170VTE33

Manufacturer Part Number
DF2170VTE33
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2170VTE33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2170VTE33
HD64F2170VTE33

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2170VTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Rev. 2.00, 03/04, page 384 of 534
Bit
3
2, 1
Bit Name
WEINTE
Initial
Value
0
All 0
R/W
R/W
R/W
Description
Program/Erase Enable
Modifies the space for the interrupt vector table, when
interrupt vector data is not read successfully during
programming/erasing flash memory or switching
between a user MAT and a user boot MAT. When this
bit is set to 1, interrupt vector data is read from address
spaces H'FF8000 to H'FF807F (on-chip RAM space),
instead of from address spaces H'000000 to H'00017F
(up to vector number 31). Therefore, make sure to set
the vector table in the on-chip RAM space before setting
this bit to 1.
The interrupt exception handling on and after vector
number 32 should not be used because the correct
vector is not read, resulting in the CPU runaway.
0: The space for the interrupt vector table is not
1: The space for the interrupt vector table is modified.
Reserved
The initial value should not be changed.
Even when interrupt vector data is not read
successfully, the interrupt exception handling up to
vector number 31 is enabled.
modified.
When interrupt vector data is not read successfully,
the operation for the interrupt exception handling
cannot be guaranteed. An occurrence of any
interrupts should be masked.

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