DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 18

MCU 3V 256K 100-TQFP

DF2170VTE33

Manufacturer Part Number
DF2170VTE33
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2170VTE33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2170VTE33
HD64F2170VTE33

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
DF2170VTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 12 Universal Serial Bus 2 (USB2)........................................................ 319
12.1 Features............................................................................................................................. 319
12.2 Input/Output Signals ......................................................................................................... 321
12.3 Register Descriptions........................................................................................................ 322
12.4 Interrupt Pins .................................................................................................................... 340
12.5 Communication Operation................................................................................................ 341
12.6 Notes on Using DMA ....................................................................................................... 358
12.7 Transition to USB Suspend Mode .................................................................................... 359
Rev. 2.00, 03/04, page xvi of xxxii
12.3.1 Interrupt Flag Register 0 (IFR0) .......................................................................... 323
12.3.2 Interrupt Select Register 0 (ISR0)........................................................................ 328
12.3.3 Interrupt Enable Register 0 (IER0) ...................................................................... 329
12.3.4 EP0o Receive Data Size Register (EPSZ0o) ....................................................... 329
12.3.5 EP1 Receive Data Size Register (EPSZ1) ........................................................... 330
12.3.6 EP0i Data Register (EPDR0i).............................................................................. 330
12.3.7 EP0o Data Register (EPDR0o) ............................................................................ 330
12.3.8 EP0s Data Register (EPDR0s) ............................................................................. 331
12.3.9 EP1 Data Register (EPDR1) ................................................................................ 331
12.3.10 EP2 Data Register (EPDR2) ................................................................................ 331
12.3.11 EP3 Data Register (EPDR3) ................................................................................ 332
12.3.12 Data Status Register 0 (DASTS0)........................................................................ 332
12.3.13 Packet Enable Register 0i (PKTE0i).................................................................... 333
12.3.14 Packet Enable Register 2 (PKTE2)...................................................................... 333
12.3.15 Packet Enable Register 3 (PKTE3)...................................................................... 333
12.3.16 FIFO Clear Register 0 (FCLR0) .......................................................................... 334
12.3.17 Endpoint Stall Register 0 (EPSTL0).................................................................... 336
12.3.18 DMA Set Register 0 (DMA0).............................................................................. 336
12.3.19 Control Register (CTRL) ..................................................................................... 337
12.3.20 Port Function Control Register 3 (PFCR3).......................................................... 338
12.3.21 USB Suspend Status Register (USBSUSP) ......................................................... 338
12.4.1 USBI0 Interrupt ................................................................................................... 340
12.4.2 USBI1 Interrupt ................................................................................................... 340
12.5.1 USB Cable Connection........................................................................................ 341
12.5.2 USB Cable Disconnection ................................................................................... 342
12.5.3 Control Transfer................................................................................................... 343
12.5.4 EP1 Bulk-Out Transfer (Dual FIFO) ................................................................... 349
12.5.5 EP2 Bulk-In Transfer (Dual FIFO)...................................................................... 351
12.5.6 EP3 Interrupt-In Transfer..................................................................................... 353
12.5.7 Processing of USB Standard Requests and Class/Vendor Requests.................... 354
12.5.8 Stall Operations ................................................................................................... 355
12.5.9 Tree Configuration............................................................................................... 358
12.5.10 Power Supply Specification................................................................................. 358
12.7.1 Suspend Signal Output......................................................................................... 359
12.7.2 Software Standby in Suspend Mode .................................................................... 361

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