DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 28

• Manufacturer Part Number: DF2170VTE33
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2170VTE33; HD64F2170VTE33

Figure 12.5 Setup Stage Operation ............................................................................................. 344
Figure 12.6 Data Stage Operation (Control-In) .......................................................................... 345
Figure 12.7 Data Stage Operation (Control-Out) ....................................................................... 346
Figure 12.8 Status Stage Operation (Control-In)........................................................................ 347
Figure 12.9 Status Stage Operation (Control-Out) ..................................................................... 348
Figure 12.10 EP1 Bulk-Out Transfer Operation......................................................................... 350
Figure 12.11 EP2 Bulk-In Transfer Operation ........................................................................... 352
Figure 12.12 EP3 Interrupt-In Transfer Operation ..................................................................... 353
Figure 12.13 Forcible Stall by Firmware.................................................................................... 356
Figure 12.14 Automatic Stall by USB Function Module............................................................ 357
Figure 12.15 PKTE2 Operation for EP2..................................................................................... 359
Figure 12.16 Enter/Recover Sequence of USB Suspend State ................................................... 360
Figure 12.17 Enter/Recover Sequence of USB Suspend State and Software Standby Mode..... 362
Figure 12.18 Connection Example of External Circuit............................................................... 367
Figure 12.19 Bus Reset Following Completion of First Bus Reset ............................................ 368
Figure 12.20 Bus Reset Detection Flow ..................................................................................... 369
Section 14 Flash Memory (0.18-µm F-ZTAT Version)
Figure 14.1 Block Diagram of Flash Memory............................................................................ 374
Figure 14.2 Mode Transition of Flash Memory.......................................................................... 375
Figure 14.3 Flash Memory Configuration .................................................................................. 377
Figure 14.4 Block Division of User MAT.................................................................................. 378
Figure 14.5 Overview of User Procedure Program .................................................................... 379
Figure 14.6 System Configuration in Boot Mode....................................................................... 402
Figure 14.7 Automatic-Bit-Rate Adjustment Operation of SCI ................................................. 402
Figure 14.8 Overview of Boot Mode State Transition Diagram................................................. 404
Figure 14.9 Programming/Erasing Overview Flow.................................................................... 405
Figure 14.10 RAM Map When Programming/Erasing is Executed ........................................... 406
Figure 14.11 Programming Procedure........................................................................................ 407
Figure 14.12 Erasing Procedure ................................................................................................. 412
Figure 14.13 Repeating Procedure of Erasing and Programming............................................... 414
Figure 14.14 Procedure for Programming User MAT in User Boot Mode ................................ 416
Figure 14.15 Procedure for Erasing User MAT in User Boot Mode .......................................... 417
Figure 14.16 Transitions to Error-Protection State..................................................................... 430
Figure 14.17 Switching between the User MAT and User Boot MAT ...................................... 431
Figure 14.18 Flowchart for Flash Memory Emulation in RAM ................................................. 432
Figure 14.19 Example of RAM Overlap Operation (256-kbyte Flash Memory)........................ 433
Figure 14.20 Memory Map in Programmer Mode...................................................................... 434
Figure 14.21 Boot Program States.............................................................................................. 436
Figure 14.22 Bit-Rate-Adjustment Sequence ............................................................................. 437
Figure 14.23 Communication Protocol Format .......................................................................... 438
Figure 14.24 New Bit-Rate Selection Sequence......................................................................... 448
Figure 14.25 Programming Sequence......................................................................................... 451
Rev. 2.00, 03/04, page xxvi of xxxii