DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 216

• Manufacturer Part Number: DF2170VTE33
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2170VTE33; HD64F2170VTE33

7.4.7
Registers during DMA Transfer Operation
DMAC register values are updated as DMA transfer processing is performed. The updated values
depend on various settings and the transfer status. The following registers and bits are updated:
DMSAR, DMDAR, DMTCR, and bits DA, BEF, and IRF in DMMDR.
DMA Source Address Register (DMSAR): When the DMSAR address is accessed as the
transfer source, after the DMSAR value is output, DMSAR is updated with the address to be
accessed next. Bits SAT1 and SAT0 in DMACR specify incrementing or decrementing. The
address is fixed when SAT1 = 0, incremented when SAT1 = 1 and SAT0 = 0, and decremented
when SAT0 = 1.
The size of the increment or decrement is determined by the size of the data transferred. When the
LWSIZE and DTSIZE bits in DMMDR = 0, the data is byte-size and the address is incremented or
decremented by 1; when LWSIZE = 0 and DTSIZE = 1, the data is word-size and the address is
incremented or decremented by 2; when LWSIZE = 1 and DTSIZE = 0, the data is longword-size
and the address is incremented or decremented by 4.
When a repeat area setting is made, the operation conforms to that setting. The upper part of the
address set for the repeat area function is fixed, and is not affected by address updating.
When DMSAR is read during a transfer operation, a longword access must be used. During a
transfer operation, DMSAR may be updated without regard to accesses from the CPU, and the
correct values may not be read if the upper and lower words are read separately. In a longword
access, the DMAC buffers the DMSAR value to ensure that the correct value is output.
Do not write to DMSAR for a channel on which a transfer operation is in progress.
DMA Destination Address Register (DMDAR): When the DMDAR address is accessed as the
transfer destination, after the DMDAR value is output, DMDAR is updated with the address to be
accessed next. Bits DAT1 and DAT0 in DMACR specify incrementing or decrementing. The
address is fixed when DAT1 = 0, incremented when DAT1 = 1 and DAT0 = 0, and decremented
when DAT0 = 1.
The size of the increment or decrement is determined by the size of the data transferred. When the
LWSIZE and DTSIZE bits in DMMDR = 0, the data is byte-size and the address is incremented or
decremented by 1; when LWSIZE = 0 and DTSIZE = 1, the data is word-size and the address is
incremented or decremented by 2; when LWSIZE = 1 and DTSIZE = 0, the data is longword-size
and the address is incremented or decremented by 4.
When a repeat area setting is made, the operation conforms to that setting. The upper part of the
address set for the repeat area function is fixed, and is not affected by address updating.
When DMDAR is read during a transfer operation, a longword access must be used. During a
transfer operation, DMDAR may be updated without regard to accesses from the CPU, and the
Rev. 2.00, 03/04, page 182 of 534