DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 414

• Manufacturer Part Number: DF2170VTE33
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2170VTE33; HD64F2170VTE33

2. Download of on-chip program
3. Initialization of programming/erasing
4. Programming/erasing execution
5. When programming/erasing is executed consecutively
Rev. 2.00, 03/04, page 380 of 534
The on-chip program is automatically downloaded by setting the flash key register (FKEY)
and the SCO bit in the flash control register (FCCS), which are programming/erasing interface
registers.
The flash memory is replaced to the embedded program storage area when downloading. Since
the flash memory cannot be read when programming/erasing, the procedure program, which is
working from download to completion of programming/erasing, must be executed in the space
other than the flash memory to be programmed/erased (for example, on-chip RAM).
Since the result of download is returned to the programming/erasing interface parameter,
whether the normal download is executed or not can be confirmed.
The operating frequency is set before execution of programming/erasing. This setting is
performed by using the programming/erasing interface parameter.
For programming/erasing execution, the FWE pin must be set to 1 to transition to user program
mode.
The program data/programming destination address is specified in 128-byte units when
programming.
The block to be erased is specified in erase-block units when erasing.
These specifications are set by using the programming/erasing interface parameter and the on-
chip program is initiated. The on-chip program is executed by using the JSR or BSR
instruction and performing the subroutine call of the specified address in the on-chip RAM.
The execution result is returned to the programming/erasing interface parameter.
The area to be programmed must be erased in advance when programming flash memory.
All interrupts are prohibited during programming and erasing. Interrupts must be masked
within the user system.
When the processing is not ended by the 128-byte programming or one-block erasure, the
program address/data and erase-block number must be updated and consecutive
programming/erasing is required.
Since the downloaded on-chip program is left in the on-chip RAM after the processing,
download and initialization are not required when the same processing is executed
consecutively.