DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 238

MCU 3V 256K 100-TQFP

DF2170VTE33

Manufacturer Part Number
DF2170VTE33
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2170VTE33

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2170VTE33
HD64F2170VTE33

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2170VTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
External Request/Cycle Steal Mode/Normal Transfer Mode: In external request mode, an
DMA transfer cycle is started a minimum of three cycles after a transfer request is accepted. The
next transfer request is accepted after the end of a one-transfer-unit DMA cycle. For external bus
space CPU cycles, at least two bus cycles are generated before the next DMA cycle.
If a transfer request is generated for another channel, an DMA cycle for the other channel is
generated before the next DMA cycle.
The DREQ pin sensing timing is different for low level sensing and falling edge sensing. The
same applies to transfer request acceptance and transfer start timing.
Figures 7.38 to 7.41 show operation timing examples for various conditions.
• No contention/dual address mode/low level sensing (see figure 7.38)
• CPU cycles/single address mode/low level sensing (see figure 7.39)
• No contention/single address mode/falling edge sensing (see figure 7.40)
• Contention with another channel/dual address mode/low level sensing (see figure 7.41)
Rev. 2.00, 03/04, page 204 of 534
φ pin
Bus cycle
Original
channel
Original
channel
Other
channel
transfer
request
(
)
Bus release
Figure 7.37 Auto Request/Burst Mode/Normal Transfer Mode
(Contention with Another Channel/Single Address Mode)
transfer cycle
DMA single
transfer cycle
DMA single
Last transfer
transfer cycle
DMA single
cycle
1 cycle
Bus
release
Other channel DMA cycle
release
Bus

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