DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 144

• Manufacturer Part Number: DF2170VTE33
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2170VTE33; HD64F2170VTE33

6.5.2
Table 6.4 shows the data buses used and valid strobes for the access spaces.
In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write,
the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half.
Table 6.4
Note: Hi-Z:
6.5.3
8-Bit, 2-State Access Space: Figure 6.11 shows the bus timing for an 8-bit, 2-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.
Rev. 2.00, 03/04, page 110 of 534
Area
8-bit access
space
16-bit access
space
Invalid: Input state; input value is ignored.
Figure 6.10 Access Sizes and Data Alignment Control (16-bit Access Space)
Valid Strobes
Basic Timing
Data Buses Used and Valid Strobes
Byte size
Byte size
Word size
Longword
size
High-impedance state
Access
Size
Byte
Byte
Word
• Even address
• Odd address
Read/
Write
Read
Write
Read
Write
Read
Write
1st bus cycle
2nd bus cycle
Address


Even
Odd
Even
Odd


D15
Upper data bus
Valid
Strobe
RD
HWR
RD
HWR
LWR
RD
HWR, LWR
D8 D7
Upper Data Bus
(D15 to D8)
Valid
Valid
Invalid
Valid
Hi-Z
Valid
Valid
Lower data bus
D0
Lower Data
Bus (D7 to D0)
Invalid
Hi-Z
Invalid
Valid
Hi-Z
Valid
Valid
Valid