DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 212
![MCU 3V 256K 100-TQFP](/photos/28/61/286108/100-tqfp_sml.jpg)
DF2170VTE33
Manufacturer Part Number
DF2170VTE33
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2170BVTE33V.pdf
(572 pages)
Specifications of DF2170VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2170VTE33
HD64F2170VTE33
HD64F2170VTE33
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2170VTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Figure 7.6 shows an example of the timing in burst mode.
7.4.5
There are two transfer modes: normal transfer mode and block transfer mode. When the activation
source is an external request, either normal transfer mode or block transfer mode can be selected.
When the activation source is an auto request, normal transfer mode is used.
Normal Transfer Mode: In normal transfer mode, transfer of one transfer unit is processed in
response to one transfer request. DMTCR functions as a 24-bit transfer counter.
The TEND signal is output only for the last DMA transfer. The DRAK signal is output each time a
transfer request is accepted and transfer processing is started. Figure 7.7 shows examples of DMA
transfer timing in normal transfer mode.
Rev. 2.00, 03/04, page 178 of 534
Bus cycle
Bus cycle
Bus cycle
Transfer Modes (Normal Transfer Mode/Block Transfer Mode)
Figure 7.7 Examples of Timing in Normal Transfer Mode
CPU
Figure 7.6 Examples of Timing in Burst Mode
(1) Dual address mode, auto request mode
(2) Single address mode, external request mode
Read
transfer cycle
CPU
DMA
Write
Auto request mode
DMAC
DMA
CPU cycle not generated
DMAC
Read
transfer cycle
Last DMA
Write
DMA
DMAC
CPU
CPU
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