DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 436
![MCU 3V 256K 100-TQFP](/photos/28/61/286108/100-tqfp_sml.jpg)
DF2170VTE33
Manufacturer Part Number
DF2170VTE33
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2170BVTE33V.pdf
(572 pages)
Specifications of DF2170VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2170VTE33
HD64F2170VTE33
HD64F2170VTE33
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2170VTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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SCI Interface Setting by Host: When boot mode is initiated, this LSI measures the low period of
asynchronous SCI-communication data (H'00), which is transmitted consecutively by the host.
The SCI transmit/receive format is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates
the bit rate of transmission by the host by means of the measured low period and transmits the bit
adjustment end sign (1 byte of H'00) to the host. The host must confirm that this bit adjustment
end sign (H'00) has been received normally and transmits 1 byte of H'55 to this LSI. When
reception is not executed normally, boot mode is initiated again (reset) and the operation described
above must be executed. The bit rate between the host and this LSI is not matched by the bit rate
of transmission by the host and system clock frequency of this LSI. To operate the SCI normally,
the transfer bit rate of the host must be set to 4,800 bps, 9,600 bps, or 19,200 bps.
The system clock frequency, which can automatically adjust the transfer bit rate of the host and
the bit rate of this LSI, is shown in table 14.7. Boot mode must be initiated in the range of this
system clock.
Rev. 2.00, 03/04, page 402 of 534
tool and program
programming
Boot
Host
data
Start
bit
Figure 14.7 Automatic-Bit-Rate Adjustment Operation of SCI
D0
Figure 14.6 System Configuration in Boot Mode
Measure low period (9 bits) (data is H'00)
Control command, program data
D1
Reply response
D2
D3
D4
analysis execution
Control command,
software (on-chip)
RxD0
TxD0
D5
On-chip SCI
D6
This LSI
D7
On-chip RAM
High period of
at least 1 bit
Stop bit
memory
Flash
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