DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 211

• Manufacturer Part Number: DF2170VTE33
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2170VTE33; HD64F2170VTE33

7.4.4
There are two bus modes: cycle steal mode and burst mode. When the activation source is an auto
request, either cycle steal mode or burst mode can be selected. When the activation source is an
external request, cycle steal mode is used.
Cycle Steal Mode: In cycle steal mode, the DMAC releases the bus at the end of each transfer of
a transfer unit (byte, word, or block). If there is a subsequent transfer request, the DMAC takes
back the bus, performs another transfer-unit transfer, and then releases the bus again. This
procedure is repeated until the transfer end condition is satisfied.
If a transfer request occurs in another channel during DMA transfer, the bus is temporarily
released, then transfer is performed on the channel for which the transfer request was issued. If
there is no external space bus request from another bus master, a one-cycle bus release interval is
inserted. For details on the operation when there are requests for a number of channels, see section
7.4.8, Channel Priority.
Figure 7.5 shows an example of the timing in cycle steal mode.
Burst Mode: In burst mode, once the DMAC acquires the bus it continues transferring data,
without releasing the bus, until the transfer end condition is satisfied. There is no burst mode in
external request mode. In burst mode, once transfer is started it is not interrupted even if there is a
transfer request from another channel with higher priority. When the burst mode channel finishes
its transfer, it releases the bus in the next cycle in the same way as in cycle steal mode.
When the DA bit is cleared to 0 in DMMDR, DMA transfer is halted. However, DMA transfer is
executed for all transfer requests generated within the DMAC up until the DA bit was cleared to 0.
If a repeat area overflow interrupt is generated, the DA bit is cleared to 0 and transfer is
terminated.
Bus Modes (Cycle Steal Mode/Burst Mode)
Transfer conditions:
Bus cycle
· Single address mode, normal transfer mode
·
· CPU internal bus master is operating in external space
low level sensing
Figure 7.5 Example of Timing in Cycle Steal Mode
CPU
CPU
DMAC
Bus returned temporarily to CPU
CPU
CPU
Rev. 2.00, 03/04, page 177 of 534
DMAC