DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 341
DF2170VTE33
Manufacturer Part Number
DF2170VTE33
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2170BVTE33V.pdf
(572 pages)
Specifications of DF2170VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2170VTE33
HD64F2170VTE33
HD64F2170VTE33
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2170VTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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11.4.3
An internal clock generated by the on-chip baud rate generator can be selected as the SCI’s serial
clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR.
11.4.4
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as shown in figure 11.4. When the operating mode, transfer format, etc., is
changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is
cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the
contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.
Set CKE1 and CKE0 bits in SCR
Clear TE and RE bits in SCR to 0
Set TE and RE bits in SCR to 1,
Set data transfer format in SMR
and set RIE, TIE, and TEIE bits
Clock
SCI Initialization (Asynchronous Mode)
<Initialization completed>
1-bit interval elapsed?
Start of initialization
Set value in BRR
(TE, RE bits = 0)
Figure 11.4 Sample SCI Initialization Flowchart
Yes
Wait
No
[1]
[2]
[3]
[4]
[1] Set the clock selection in SCR.
[2] Set the data transfer format in SMR.
[3] Write a value corresponding to the
[4] Wait at least one bit interval, then
Be sure to clear bits RIE, TIE, and
TEIE, and bits TE and
RE, to 0.
When the clock is selected in
asynchronous mode, it is output
immediately after SCR settings are
made.
bit rate to BRR. (Not necessary if
an external clock is used.)
set the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, and TEIE bits.
Setting the TE and RE bits enables
the TxD and RxD pins to be used.
Rev. 2.00, 03/04, page 307 of 534
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