DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 442

• Manufacturer Part Number: DF2170VTE33
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2170VTE33; HD64F2170VTE33

When less than 128-byte programming is performed, data must total 128 bytes by adding the
invalid data. If the dummy data to be added is H'FF, the program processing period can be
shortened.
1. Select the on-chip program to be downloaded and specify a download destination
2. Program H'A5 in FKEY
3. 1 is set to the SCO bit of FCCS and then download is executed.
Rev. 2.00, 03/04, page 408 of 534
When the PPVS bit of FPCS is set to 1, the programming program is selected. Several
programming/erasing programs cannot be selected at one time. If several programs are set,
download is not performed and a download error is returned to the SS bit in DPFR. The start
address of a download destination is specified by FTDAR.
If H'A5 is not written to FKEY for protection, 1 cannot be set to the SCO bit for download
request.
To set 1 to the SCO bit, the following conditions must be satisfied.
 H'A5 is written to FKEY.
 The SCO bit writing is executed in the on-chip RAM.
When the SCO bit is set to 1, download is started automatically. When the SCO bit is returned
to the user procedure program, the SCO is cleared to 0. Therefore, the SCO bit cannot be
confirmed to be 1 in the user procedure program.
The download result can be confirmed only by the return value of DPFR. Before the SCO bit is
set to 1, incorrect determination must be prevented by setting the one byte of the start address
(to be used as DPFR) specified by FTDAR to a value other than the return value (H'FF).
When download is executed, particular interrupt processing, which is accompanied by the bank
switch as described below, is performed as an internal microcomputer processing. Four NOP
instructions are executed immediately after the instructions that set the SCO bit to 1.
 The user-MAT space is switched to the on-chip program storage area.
 After the selection condition of the download program and the FTDAR setting are checked,
 The SCO bit in FCCS is cleared to 0.
 The return value is set to the DPFR parameter.
 After the on-chip program storage area is returned to the user-MAT space, the user
 In the download processing, the values of general registers of the CPU are held.
 In the download processing, any interrupts are not accepted. However, interrupt requests
 When the level-detection interrupt requests are to be held, interrupts must be input until the
the transfer processing to the on-chip RAM specified by FTDAR is executed.
procedure program is returned.
are held. Therefore, when the user procedure program is returned, the interrupts occur.
download is ended.