DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 158
![MCU 3V 256K 100-TQFP](/photos/28/61/286108/100-tqfp_sml.jpg)
DF2170VTE33
Manufacturer Part Number
DF2170VTE33
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2170BVTE33V.pdf
(572 pages)
Specifications of DF2170VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2170VTE33
HD64F2170VTE33
HD64F2170VTE33
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2170VTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.6.5
Figure 6.22 shows the basic access timing for DRAM space.
The four states of the basic timing consist of one T
output cycle) state, and two T
When DRAM space is accessed, the RD signal is output as the OE signal for DRAM. When
connecting DRAM provided with an EDO page mode, the OE signal should be connected to the
(OE) pin of the DRAM.
Rev. 2.00, 03/04, page 124 of 534
Read
Write
Basic Timing
Figure 6.22 DRAM Basic Access Timing (RAST = 0, CAST = 0)
φ
Address bus
Data bus
Data bus
(
(
(
(
(
,
)
)
)
)
)
c1
and T
c2
T
(column address output cycle) states.
p
Row address
High
High
p
T
(precharge cycle) state, one T
r
T
c1
Column address
T
c2
r
(row address
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