DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 213

• Manufacturer Part Number: DF2170VTE33
• Description: MCU 3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: HD64F2170VTE33; HD64F2170VTE33

Block Transfer Mode: In block transfer mode, the number of bytes, words, or longwords
specified by the block size is transferred in response to one transfer request. The upper 8 bits of
DMTCR specify the block size, and the lower 16 bits function as a 16-bit transfer counter. A block
size of 1 to 256 can be specified.
During transfer of a block, transfer requests for other higher-priority channels are held pending.
When transfer of one block is completed, the bus is released in the next cycle.
Address register values are updated in the same way as in normal mode. There is no function for
restoring the initial address register values after each block transfer.
The TEND signal is output for each block transfer in the DMA transfer cycle in which the block
ends. The DRAK signal is output once for one transfer request (for transfer of one block).
Caution is required when setting the repeat area overflow interrupt of the repeat area function in
block transfer mode. See section 7.4.6, Repeat Area Function, for details. Block transfer is aborted
if an NMI interrupt is generated. See section 7.4.12, Ending DMA Transfer, for details.
Figure 7.8 shows an example of DMA transfer timing in block transfer mode.
7.4.6
The DMAC has a function for designating a repeat area for source addresses and/or destination
addresses. When a repeat area is designated, the address register values repeat within the range
specified as the repeat area. Normally, when a ring buffer is involved in a transfer, an operation is
required to restore the address register value to the buffer start address each time the address
register value is the last address in the buffer (i.e. when ring buffer address overflow occurs), but if
Transfer conditions:
Bus cycle
· Single address mode
· Block size (DMTCR[23:16]) = 3
Repeat Area Function
CPU
Figure 7.8 Example of Timing in Block Transfer Mode
CPU
CPU
DMAC
One-block transfer cycle
CPU cycle not generated
DMAC
Rev. 2.00, 03/04, page 179 of 534
DMAC
CPU