r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 91

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r5s72060w200fpv

Manufacturer Part Number
r5s72060w200fpv
Description
32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

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2.5
The CPU has five processing states: reset, exception handling, bus-released, program execution,
and power-down. Figure 2.6 shows the transitions between the states.
Interrupt source or
DMA address error occurs
Instruction
BXOR.B
Processing States
#imm3,@(disp12,Rn) 0011nnnn0iii1001
Bus request
generated
Bus-released state
Figure 2.6 Transitions between Processing States
Sleep mode
Power-on reset from any state
Bus request
cleared
Bus request
cleared
Instruction Code
0110dddddddddddd
Power-on reset state
Bus request
generated
Bus request
generated
Bus request
cleared
STBY bit cleared
for SLEEP
instruction
Exception
handling
Operation
(imm of (disp + Rn)) ^ T → T
Program execution state
source
occurs
Reset canceled
handling state
Exception
Exception
handling
ends
Rev. 2.00 Dec. 09, 2005 Page 67 of 1152
Manual reset from any state
Manual reset state
Software standby mode
STBY bit set
for SLEEP
instruction
Execu-
tion
Cycles T Bit
3
Ope-
ration
result
Reset state
Power-down state
NMI interrupt or
IRQ interrupt occurs
REJ09B0191-0200
SH2,
SH2E SH4 SH-2A
Section 2 CPU
Compatibility
Yes

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