r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 399

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Note:
Bit
1
0
*
Bit Name
TE
DE
Only 0 can be written to clear the flag after 1 is read.
Initial
Value
0
0
R/W
R/(W)* Transfer End Flag
R/W
Descriptions
This bit is set to 1 when DMATCR becomes 0 and
DMA transfer ends.
The TE bit is not set to 1 in the following cases.
•
•
To clear the TE bit, write 0 after reading TE = 1.
Even if the DE bit is set to 1 while this bit is set to 1,
transfer is not enabled.
0: During the DMA transfer or DMA transfer has been
[Clearing condition]
•
1: DMA transfer ends by the specified count
DMA Enable
Enables or disables the DMA transfer. In auto request
mode, DMA transfer starts by setting the DE bit and
DME bit in DMAOR to 1. In this case, all of the bits
TE, NMIF in DMAOR, and AE must be 0. In an
external request or peripheral module request, DMA
transfer starts if DMA transfer request is generated by
the devices or peripheral modules after setting the
bits DE and DME to 1. In this case, however, all of the
bits TE, NMIF, and AE must be 0 as in the case of
auto request mode. Clearing the DE bit to 0 can
terminate the DMA transfer.
0: DMA transfer disabled
1: DMA transfer enabled
terminated
(DMATCR = 0)
DMA transfer ends due to an NMI interrupt or
DMA address error before DMATCR becomes 0.
DMA transfer is ended by clearing the DE bit and
DME bit in DMA operation register (DMAOR).
Writing 0 after reading TE = 1
Section 9 Direct Memory Access Controller (DMAC)
Rev. 2.00 Dec. 09, 2005 Page 375 of 1152
REJ09B0191-0200