r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 229

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Note:
8.3.2
In this LSI, the data bus width of area 0 and the initial data bus width of areas 1 to 8 can be set to
8, 16, or 32 bits through external pins during a power-on reset. The bus width of area 0 cannot be
modified after a power-on reset. The initial data bus width of areas 1 to 8 is set to the same size as
that of area 0, but can be modified through register settings during program execution. Note that
the selectable data bus widths may be limited depending on the connected memory type.
After a power-on reset, the LSI starts execution of the program stored in the external memory
allocated in area 0. Since ROM is assumed as the external memory in area 0, minimum pin
functions such as the address bus, data bus, CS0, and RD are available. The sample access
waveforms shown in this section include other pins such as BS, RD/WR, and WEn, which are
available after they are selected through the pin function controller. Before pin function settings
are completed by a program, only read access to area 0 is allowed; do not perform any other
access. The A1 and A0 pin settings are also necessary to modify the bus width of an area other
than area 0 into 8 or 16 bits after the LSI is started with a 32-bit data bus.
For details on pin function settings, see section 19, Pin Function Controller (PFC).
Table 8.3
Internal Address
H'40000000 to H'7FFFFFFF CS8
H'80000000 to H'FFFBFFFF Other
H'FFFC0000 to H'FFFFFFFF Other
MD2
1
0
*
Data Bus Width and Pin Function Setting in Each Area
For the on-chip RAM space, access the addresses shown in section 21, On-Chip RAM.
For the on-chip peripheral module space, access the addresses shown in section 24,
List of Registers. Do not access addresses which are not described in these sections.
Otherwise, the correct operation cannot be guaranteed.
Correspondence between External Pins (MD2 and MD0) and Data Bus Width
MD0
1
0
1
0
Space Memory to be Connected
Normal space, SRAM with byte selection
On-chip RAM, reserved area*
On-chip peripheral modules, reserved area*
Data Bus Width
32 bits
16 bits
8 bits
Reserved (setting prohibited)
Rev. 2.00 Dec. 09, 2005 Page 205 of 1152
Section 8 Bus State Controller (BSC)
Cache
Cache-disabled
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REJ09B0191-0200