r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 214

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 7 Cache
7.3.2
(1)
In a read access, data is transferred from the cache to the CPU. LRU is updated so that the hit way
is the latest.
(2)
An external bus cycle starts and the entry is updated. The way replaced follows table 7.4. Entries
are updated in 16-byte units. When the desired data that caused the miss is loaded from external
memory to the cache, the data is transferred to the CPU in parallel with being loaded to the cache.
When it is loaded in the cache, the V bit is set to 1, and LRU is updated so that the replaced way
becomes the latest. In operand cache, the U bit is additionally cleared to 0. When the U bit of the
entry to be replaced by updating the entry in write-back mode is 1, the cache update cycle starts
after the entry is transferred to the write-back buffer. After the cache completes its update cycle,
the write-back buffer writes the entry back to the memory. The write-back unit is 16 bytes.
7.3.3
(1)
LRU is updated so that the hit way becomes the latest. The contents in other caches are not
modified. No data is transferred to the CPU.
(2)
No data is transferred to the CPU. The way to be replaced follows table 7.3. Other operations are
the same in case of read miss.
Rev. 2.00 Dec. 09, 2005 Page 190 of 1152
REJ09B0191-0200
Read Hit
Read Miss
Prefetch Hit
Prefetch Miss
Read Access
Prefetch Operation (Only for Operand Cache)