r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 1155

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Item
6.5 Usage Notes
7.1.1 Cache Structure
(1) Address Array
7.4.4 Notes
8.4.2 CSn Space Bus Control
Register (CSnBCR) (n = 0 to 8)
Page Revision (See Manual for Details)
178
180
197
215
Added.
9. Do not set a user break before instruction execution
10. Do not set a user break both before instruction
Amended.
In this LSI, the addresses of the cache-enabled space
are H'00000000 to H'1FFFFFFF (see section 8, Bus
State Controller (BSC)), and therefore the upper three
bits of the tag address are cleared to 0.
Added.
3. Memory-mapped cache can be accessed only by the
Amended.
Bit
10, 9
CPU and not by the DMAC. Registers can be
accessed by the CPU and the DMAC.
for the instruction following the DIVU or DIVS
instruction. If a user break before instruction
execution is set for the instruction following the
DIVU or DIVS instruction and an exception or
interrupt occurs during execution of the DIVU or
DIVS instruction, a user break occurs before
instruction execution even though execution of the
DIVU or DIVS instruction is halted.
execution and after instruction execution for
instruction of the same address. If, for example, a
user break before instruction execution on channel
0 and a user break after instruction on channel 1
are set at the instruction of the same address, the
condition match flag for the channel 1 is set even
though a user break on channel 0 occurs before
instruction execution.
Bit Name
BSZ[1:0]
Rev. 2.00 Dec. 09, 2005 Page 1131 of 1152
Description
6. If area 0 is specified as
clocked synchronous burst
ROM space, the bus width
can be specified as either
16 bits or 32 bits.
REJ09B0191-0200