r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 761

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Bit
6
Bit Name
TEND
Initial
Value
1
R/W
R/(W)* Transmit End
Section 15 Serial Communication Interface with FIFO (SCIF)
Description
Indicates that when the last bit of a serial character
was transmitted, SCFTDR did not contain valid data,
so transmission has ended.
0: Transmission is in progress
[Clearing condition]
•
1: End of transmission
[Setting conditions]
•
•
•
Note:
TEND is cleared to 0 when 0 is written after 1 is
read from TEND after transmit data is written in
SCFTDR*
TEND is set to 1 when the chip is a power-on
reset
TEND is set to 1 when TE is cleared to 0 in the
serial control register (SCSCR)
TEND is set to 1 when SCFTDR does not contain
receive data when the last bit of a one-byte serial
character is transmitted
1. Do not use this bit as a transmit end flag
when the DMAC writes data to SCFTDR
due to a TXI interrupt request.
1
Rev. 2.00 Dec. 09, 2005 Page 737 of 1152
REJ09B0191-0200