r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 190

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r5s72060w200fpv

Manufacturer Part Number
r5s72060w200fpv
Description
32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

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0
Section 6 User Break Controller (UBC)
[Legend]
x:
Rev. 2.00 Dec. 09, 2005 Page 166 of 1152
REJ09B0191-0200
Bit
7, 6
5, 4
3, 2
1, 0
Don't care
Bit Name
CD[1:0]
ID[1:0]
RW[1:0]
SZ[1:0]
Initial
Value
00
00
00
00
R/W
R/W
R/W
R/W
R/W
Description
C Bus Cycle/I Bus Cycle Select
Select the C bus cycle or I bus cycle as the bus cycle
of the break condition.
00: Condition comparison is not performed
01: Break condition is the C bus (F bus or M bus) cycle
10: Break condition is the I bus cycle
11: Break condition is the C bus (F bus or M bus) cycle
Instruction Fetch/Data Access Select
Select the instruction fetch cycle or data access cycle
as the bus cycle of the break condition. If the
instruction fetch cycle is selected, select the C bus
cycle.
00: Condition comparison is not performed
01: Break condition is the instruction fetch cycle
10: Break condition is the data access cycle
11: Break condition is the instruction fetch cycle or
Read/Write Select
Select the read cycle or write cycle as the bus cycle of
the break condition.
00: Condition comparison is not performed
01: Break condition is the read cycle
10: Break condition is the write cycle
11: Break condition is the read cycle or write cycle
Operand Size Select
Select the operand size of the bus cycle for the break
condition.
00: Break condition does not include operand size
01: Break condition is byte access
10: Break condition is word access
11: Break condition is longword access
data access cycle

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