r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 324

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 8 Bus State Controller (BSC)
(4)
A read access ends in one cycle when data exists in a cache-disabled space and the data bus width
is larger than or equal to the access size. As the SDRAM is set to the burst read with the burst
length 1, only the required data is output. A read access that ends in one cycle is called single read.
Figure 8.20 shows the single read basic timing.
Rev. 2.00 Dec. 09, 2005 Page 300 of 1152
REJ09B0191-0200
Single Read
Figure 8.20 Basic Timing for Single Read (CAS Latency 1, Auto Pre-Charge)
RASL, RASU
CASL, CASU
A12/A11*
D31 to D0
A25 to A0
DACKn*
RD/WR
DQMxx
CKIO
CSn
BS
1
2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Tr
Tc1
Td1
Tde
(Tap)