r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 311

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r5s72060w200fpv

Manufacturer Part Number
r5s72060w200fpv
Description
32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

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0
Table 8.9
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
BSZ
[1:0]
11 (32 bits)
Output Pin of
This LSI
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Example of connected memory
256-Mbit product (2 Mwords × 32 bits × 4 banks, column 9 bits product): 1
128-Mbit product (2 Mwords × 16 bits × 4 banks, column 9 bits product): 2
2. Bank address specification
3. Only the RASL pin is asserted because the A25 pin specified the bank address. RASU
access mode.
is not asserted.
Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address
Multiplex Output (2)-1
A2/3
ROW
[1:0]
01 (12 bits)
Row Address
Output Cycle
A26
A25
A24*
A23*
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
2
2
Setting
A2/3
COL
[1:0]
01 (9 bits)
Column Address
Output Cycle
A17
A16
A24*
A23*
A13
L/H*
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
2
2
SDRAM Pin
A13 (BA1)
A12 (BA0)
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Rev. 2.00 Dec. 09, 2005 Page 287 of 1152
Section 8 Bus State Controller (BSC)
Function
Unused
Specifies bank
Address
Specifies
address/precharge
Address
Unused
REJ09B0191-0200

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