r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 755

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

15.3.6
SCSCR operates the SCIF transmitter/receiver, enables/disables interrupt requests, and selects the
transmit/receive clock source. The CPU can always read and write to SCSCR. SCSCR is
initialized to H'0000 by a power-on reset.
Initial value:
Bit
15 to 8
7
R/W:
Bit:
Serial Control Register (SCSCR)
Bit Name

TIE
15
R
0
-
14
R
0
-
13
R
0
-
Initial
Value
All 0
0
12
R
0
-
11
R
0
-
R/W
R
R/W
10
R
0
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmit Interrupt Enable
Enables or disables the transmit-FIFO-data-empty
interrupt (TXI) requested when the serial transmit data
is transferred from the transmit FIFO data register
(SCFTDR) to the transmit shift register (SCTSR), when
the quantity of data in the transmit FIFO register
becomes less than the specified number of
transmission triggers, and when the TDFE flag in the
serial status register (SCFSR) is set to1.
0: Transmit-FIFO-data-empty interrupt request (TXI) is
1: Transmit-FIFO-data-empty interrupt request (TXI) is
Note: * The TXI interrupt request can be cleared by
Section 15 Serial Communication Interface with FIFO (SCIF)
disabled
enabled*
R
9
0
-
writing a greater quantity of transmit data than
the specified transmission trigger number to
SCFTDR and by clearing TDFE to 0 after
reading 1 from TDFE, or can be cleared by
clearing TIE to 0.
R
8
0
-
R/W
TIE
7
0
Rev. 2.00 Dec. 09, 2005 Page 731 of 1152
R/W
RIE
6
0
R/W
TE
5
0
R/W
RE
4
0
R/W
REIE
3
0
REJ09B0191-0200
R
2
0
-
R/W
1
0
CKE[1:0]
R/W
0
0