r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 206

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 7 Cache
7.2
The cache has the following registers.
Table 7.2
7.2.1
The instruction cache is enabled or disabled using the ICE bit. The ICF bit controls disabling of all
instruction cache entries. The operand cache is enabled or disabled using the OCE bit. The OCF
bit controls disabling of all operand cache entries. The WT bit selects either write-through mode or
write-back mode for operand cache.
Programs that change the contents of CCR1 should be placed in a cache-disabled space, and a
cache-enabled space should be accessed after reading the contents of CCR1.
CCR1 is initialized to H'00000000 by a power-on reset but not initialized by a manual reset or in
software standby mode.
Initial value:
Initial value:
Rev. 2.00 Dec. 09, 2005 Page 182 of 1152
REJ09B0191-0200
Register Name
Cache control register 1
Cache control register 2
R/W:
R/W:
Bit:
Bit:
Register Descriptions
Cache Control Register 1 (CCR1)
31
15
R
R
0
0
-
-
Register Configuration
30
14
R
R
0
0
-
-
29
13
R
R
0
0
-
-
Abbreviation
CCR1
CCR2
28
12
R
R
0
0
-
-
R/W
ICF
27
11
R
0
0
-
26
10
R
R
0
0
-
-
R/W
R/W
R/W
25
R
R
0
9
0
-
-
R/W
ICE
24
R
0
8
0
-
Initial Value
H'00000000
H'00000000
23
R
R
0
7
0
-
-
22
R
R
0
6
0
-
-
Address
H'FFFC1000 32
H'FFFC1004 32
21
R
R
0
5
0
-
-
20
R
R
0
4
0
-
-
R/W
OCF
19
R
0
3
0
-
Access Size
18
R
R
0
2
0
-
-
R/W
WT
17
R
0
1
0
-
R/W
OCE
16
R
0
0
0
-