r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 804

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 15 Serial Communication Interface with FIFO (SCIF)
15.5
The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI),
receive FIFO data full (RXI), and break (BRI).
Table 15.12 shows the interrupt sources and their order of priority. The interrupt sources are
enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt
request is sent to the interrupt controller for each of these interrupt sources.
When a TXI request is enabled by the TIE bit and the TDFE flag in the serial status register
(SCFSR) is set to 1, a TXI interrupt request is generated. The DMAC can be activated and data
transfer performed by this TXI interrupt request. At this time, an interrupt request is not sent to the
CPU.
When an RXI request is enabled by the RIE bit and the RDF flag or the DR flag in SCFSR is set
to 1, an RXI interrupt request is generated. The DMAC can be activated and data transfer
performed by this RXI interrupt request. At this time, an interrupt request is not sent to the CPU.
The RXI interrupt request caused by the DR flag is generated only in asynchronous mode.
When the RIE bit is set to 0 and the REIE bit is set to 1, the SCIF requests only an ERI interrupt
without requesting an RXI interrupt.
The TXI indicates that transmit data can be written, and the RXI indicates that there is receive data
in SCFRDR.
Table 15.12 SCIF Interrupt Sources
Rev. 2.00 Dec. 09, 2005 Page 780 of 1152
REJ09B0191-0200
Interrupt
Source
BRI
ERI
RXI
TXI
SCIF Interrupts
Description
Interrupt initiated by break (BRK) or overrun error
(ORER)
Interrupt initiated by receive error (ER)
Interrupt initiated by receive FIFO data full (RDF) or
data ready (DR)
Interrupt initiated by transmit FIFO data empty
(TDFE)
DMAC
Activation
Not possible
Not possible
Possible
Possible
Priority on
Reset Release
High
Low