r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 175

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Figure 5.12 shows the timing for saving to a register bank. Saving to a register bank takes place
between the start of interrupt exception handling and the start of fetching the first instruction in the
interrupt exception service routine.
(2)
The RESBANK (restore from register bank) instruction is used to restore data saved in a register
bank. After restoring data from the register banks with the RESBANK instruction at the end of the
interrupt exception service routine, execute the RTE instruction to return from interrupt exception
service routine.
IRQ
Instruction (instruction replacing
interrupt exception handling)
Overrun fetch
First instruction in interrupt exception
service routine
[Legend]
m1:
m2:
m3:
Restoration from Bank
Vector address read
Saving of SR (stack)
Saving of PC (stack)
2 Icyc + 3 Bcyc + 1 Pcyc
Figure 5.12 Bank Save Timing
F
D
F
3 Icyc
3 Icyc + m1 + m2
E
Saved to bank
E
(1) VTO, PR, GBR, MACL
m1
M
Rev. 2.00 Dec. 09, 2005 Page 151 of 1152
(2) R12, R13, R14, MACH
m2
M
Section 5 Interrupt Controller (INTC)
(3) R8, R9, R10, R11
m3
M
F
(4) R4, R5, R6, R7
E
D
(5) R0, R1, R2, R3
E
REJ09B0191-0200