r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 695

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

12.3.2
OCSR1 is a 16-bit readable/writable register that controls the enable/disable of both output level
comparison and interrupts, and indicates status.
Initial value:
Bit
15
14 to 10 
9
8
Notes:
R/W:
Bit:
1.
2.
Output Level Control/Status Register 1 (OCSR1)
R/(W)*
Bit Name
OSF1
OCE1
OIE1
OSF1
Only 0 can be written to clear the flag after 1 is read.
Can be modified only once after a power-on reset.
15
0
1
14
R
0
-
Initial
Value
0
All 0
0
0
13
R
0
-
12
R
0
-
R/W
R/(W)*
R
R/W*
R/W
11
R
0
-
2
1
10
R
0
-
Description
Output Short Flag 1
Indicates that any one of the three pairs of MTU2 2-
phase outputs to be compared has simultaneously
become an active level.
[Clearing condition]
•
[Setting condition]
•
Reserved
These bits are always read as 0. The write value should
always be 0.
Output Short High-Impedance Enable 1
Specifies whether to place the pins in high-impedance
state when the OSF1 bit in OCSR1 is set to 1.
0: Does not place the pins in high-impedance state
1: Places the pins in high-impedance state
Output Short Interrupt Enable 1
Enables or disables interrupt requests when the OSF1 bit
in OCSR is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
R/W*
OCE1
By writing 0 to OSF1 after reading OSF1 = 1
When any one of the three pairs of 2-phase outputs
has simultaneously become an active level
9
0
2
OIE1
R/W
8
0
R
7
0
-
Rev. 2.00 Dec. 09, 2005 Page 671 of 1152
Section 12 Port Output Enable 2 (POE2)
R
6
0
-
R
5
0
-
R
4
0
-
R
3
0
-
REJ09B0191-0200
R
2
0
-
R
1
0
-
R
0
0
-