r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 292

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 8 Bus State Controller (BSC)
8.5.2
(1)
For access to a normal space, this LSI uses strobe signal output in consideration of the fact that
mainly static RAM will be directly connected. When using SRAM with a byte-selection pin, see
section 8.5.8, SRAM Interface with Byte Selection. Figure 8.3 shows the basic timings of normal
space access. A no-wait normal access is completed in two cycles. The BS signal is asserted for
one cycle to indicate the start of a bus cycle.
There is no access size specification when reading. The correct access start address is output in the
least significant bit of the address, but since there is no access size specification, 32 bits are always
Rev. 2.00 Dec. 09, 2005 Page 268 of 1152
REJ09B0191-0200
Basic Timing
Normal Space Interface
Figure 8.3 Normal Space Basic Access Timing (Access Wait 0)
Note: * The waveform for DACKn is when active low is specified.
Write
Read
A25 to A0
RD/WR
D31 to D0
RD/WR
D31 to D0
DACKn
CKIO
WEn
CSn
RD
BS
*
T1
T2